-
- News
- Books
Featured Books
- design007 Magazine
Latest Issues
Current IssueLevel Up Your Design Skills
This month, our contributors discuss the PCB design classes available at IPC APEX EXPO 2024. As they explain, these courses cover everything from the basics of design through avoiding over-constraining high-speed boards, and so much more!
Opportunities and Challenges
In this issue, our expert contributors discuss the many opportunities and challenges in the PCB design community, and what can be done to grow the numbers of PCB designers—and design instructors.
Embedded Design Techniques
Our expert contributors provide the knowledge this month that designers need to be aware of to make intelligent, educated decisions about embedded design. Many design and manufacturing hurdles can trip up designers who are new to this technology.
- Articles
- Columns
Search Console
- Links
- Events
||| MENU - design007 Magazine
HyperLynx: There’s an App for That
August 5, 2022 | I-Connect007 Editorial TeamEstimated reading time: 10 minutes
When we’re laying down power planes, we’re asking, “Do we have enough metal to carry the current needed, and will neckdowns cause problems due to excessive voltage drop?” The DC drop app will allow you to analyze and visualize current flow under steady state conditions, so you can quickly identify and correct potential problems.
When we’re designing an AC power delivery network (PDN), we’re placing decoupling capacitors, and we’re asking, “Do we have enough capacitors, with the right values, close enough to the devices they need to service?” The traditional approach to placing decoupling capacitors has often been called “sprinkle and pray,” which results in overdesign and higher manufacturing costs. Being able to determine how many capacitors are actually needed makes the process more reliable and frees valuable board space that would have been occupied by unnecessary capacitors.
Pulse response analysis considers a group of signals that should have nearly identical electrical characteristics to see if there are any outliers. This is first-order signal integrity; I don’t need the exact driver model; I just need a technology model with about the right impedance at about the right edge rate. That makes the setup and simulation process much simpler. I can quickly analyze a group of related signals (think DDR data or address bus) to see if anything stands out, then go from there.
Johnson: This is the “signal and power integrity for the average engineer” you’ve been talking about in past interviews?
Westerhoff: Right. It’s based on reframing the way we typically think about signal and power integrity. Typically, we’re told that signal integrity and power integrity need to be detailed, quantitative, and exact, down to the millivolt or picosecond. That results in a process that can only be performed by SI/PI experts. The analysis we perform with design apps is more of a qualitative approach. We’re running first-order analysis during layout to tune things as we lay them down, identifying and resolving obvious problems as we go. Remember, design apps aren’t trying to perform signoff analysis; we assume the normal signoff process still applies.
Regression apps are more what we typically consider as signal integrity because they’re specific and quantitative. They’re also different in that they are standards-based and focus on spec compliance instead of device-specific performance. It’s much easier to determine whether a channel is compliant with a spec because all you need is the layout database and which protocol you want to analyze it for; everything else is already known. Traditional serial channel analysis involves vendor IBIS-AMI models, which is a much more complicated and case-dependent proposition. Protocol compliance analysis is well-defined once you know the protocol, so it can be automated.
The extraction and electromagnetic modeling process for serial channel compliance is pretty complex, so this isn’t a “while you wait” process; it’s an automated, overnight run. Load the layout database at the end of the day, start the compliance app, and have a report ready for the next morning. That’s the workflow.
Setting up a regression app is more involved, so it can make sense to have an SI/PI expert set up the initial run and save that setup to a library. That makes sure that everything is configured correctly to ensure a correct final result. Once the setup is in the library, the designer can rerun the analysis as often as they need at the push of a button.
Johnson: How accurate are the results we’re talking about here? How well do HyperLynx Apps results compare to HyperLynx?
Westerhoff: Excellent question. As we said, signal and power integrity are traditionally all about accuracy. The important point here is that HyperLynx Apps are HyperLynx. We’ve just created a simpler front-end for specific tasks. We’re building on the infrastructure HyperLynx already has, so the accuracy and analytical capabilities are the same. In some cases, the app calls the automated flows that have existed in HyperLynx for some time now.
Johnson: What happens if a designer runs across a problem that they can’t resolve using the app?
Westerhoff: Good point. We’re giving PCB and hardware designers the ability to run analysis themselves, but the design problems can still be quite complex. They eventually will run into something that they can’t resolve, so then what? Remember that HyperLynx Apps use the same database and analytical methods as traditional HyperLynx. That means that when a designer runs analysis and gets stuck, the HyperLynx simulation setup and results already exist. An experienced user can open up the project with traditional HyperLynx and dig right in.
Johnson: The designer escalates the problem, so the SI/PI experts can take a look at it?
Westerhoff: Right, but the SI/PI experts get the problem handed to them on a silver platter, with a complete simulation setup and results available. It’s all ready to go.
Johnson: When will these HyperLynx Apps be available?
Westerhoff: We began shipping HyperLynx Apps with the 2.11 release this March. We’ve been working with select customers on this concept for a while, and we’ve just opened it up for general use.
Johnson: Thanks for speaking with me, Todd.
Westerhoff: Thank you, Nolan.
Additional content from Siemens Digital Industries Software:
Page 2 of 2Suggested Items
iNEMI Packaging Tech Topic Series: Role of EDA in Advanced Semiconductor Packaging
04/26/2024 | iNEMIAdvanced semiconductor packaging with heterogenous integration has made on-package integration of multiple chips a crucial part of finding alternatives to transistor scaling. Historically, EDA tools for front-end and back-end design have evolved separately; however, design complexity and the increased number of die-to-die or die-to-substrate interconnections has led to the need for EDA tools that can support integration of overall design planning, implementation, and system analysis in a single cockpit.
Cadence, TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
04/25/2024 | Cadence Design SystemsCadence Design Systems, Inc. and TSMC have extended their longstanding collaboration by announcing a broad range of innovative technology advancements to accelerate design, including developments ranging from 3D-IC and advanced process nodes to design IP and photonics.
Ansys, TSMC Enable a Multiphysics Platform for Optics and Photonics, Addressing Needs of AI, HPC Silicon Systems
04/25/2024 | PRNewswireAnsys announced a collaboration with TSMC on multiphysics software for TSMC's Compact Universal Photonic Engines (COUPE). COUPE is a cutting-edge Silicon Photonics (SiPh) integration system and Co-Packaged Optics platform that mitigates coupling loss while significantly accelerating chip-to-chip and machine-to-machine communication.
Siemens’ Breakthrough Veloce CS Transforms Emulation and Prototyping with Three Novel Products
04/24/2024 | Siemens Digital Industries SoftwareSiemens Digital Industries Software launched the Veloce™ CS hardware-assisted verification and validation system. In a first for the EDA (Electronic Design Automation) industry, Veloce CS incorporates hardware emulation, enterprise prototyping and software prototyping and is built on two highly advanced integrated circuits (ICs) – Siemens’ new, purpose-built Crystal accelerator chip for emulation and the AMD Versal™ Premium VP1902 FPGA adaptive SoC (System-on-a-chip) for enterprise and software prototyping.
Listen Up! The Intricacies of PCB Drilling Detailed in New Podcast Episode
04/25/2024 | I-Connect007In episode 5 of the podcast series, On the Line With: Designing for Reality, Nolan Johnson and Matt Stevenson continue down the manufacturing process, this time focusing on the post-lamination drilling process for PCBs. Matt and Nolan delve into the intricacies of the PCB drilling process, highlighting the importance of hole quality, drill parameters, and design optimization to ensure smooth manufacturing. The conversation covers topics such as drill bit sizes, aspect ratios, vias, challenges in drilling, and ways to enhance efficiency in the drilling department.