Keysight Enables Advanced Pre-Tapeout Silicon Prototyping Using Digital Twin Signaling
May 11, 2023 | Business WireEstimated reading time: 2 minutes
Keysight Technologies, Inc. released a new Universal Signal Processing Architecture (USPA) prototyping platform, enabling semiconductor companies to conduct complete chip prototyping and verification, pre-tapeout, in a real-time development environment integrating digital twins of fully-compliant, standards-based signals.
The final step of the chip design process, known as the silicon tapeout, is an increasingly expensive procedure that leaves little room for design failure. If a design fails following the tapeout, chip makers must start over again with a new “re-spin” that can take 12 months or longer to complete. In addition to tying up valuable research and development resources, these chip redesigns can potentially cause the chip maker to miss a narrow time-to-market window.
To reduce the risks of design failures and expensive re-spins, the Keysight USPA platform provides chip designers and engineers with complete digital twin signaling to verify designs before they are committed to silicon. The USPA platform offers designers an alternative to proprietary custom prototyping systems by integrating ultrafast signal converters with a high performance, completely modular field-programmable gate array (FPGA) prototyping system.
The unique USPA prototyping platform offers the following benefits:
- Supports the highest performance optoelectronic development projects with digital-to-analog converter (DAC) and analog-to-digital converter (ADC) interfaces that emulate signals at full speed, up to 68 GS/s (ADC) and 72 GS/s (DAC).
- Provides a broad range of input / output interfaces that are suitable for applications including 6G wireless development, digital radio frequency memory, advanced physics research, and high-speed data acquisition applications, such as radar and radio astronomy.
- Offers flexibility with two configurations, including a pre-configured system for single channel transceiver applications and a fully configurable set of modular components that can be combined to support a wide range of single and multi-channel applications. In addition, the pre-configured system can be expanded with additional components that leverage the modularity, scalability, and cost-effective reusability of the platform architecture.
Hong Jiang, CEO Avance Semi, Inc., said: “When we began work on our first ASIC for the coherent fiber communication market, we understood that we might only have one chance to get it right and that a second tapeout would be both prohibitively expensive and so time-consuming that we could miss our narrow time-to-market window. With Keysight’s USPA platform and our system integration effort, we can optimize and verify our design in real-time as it progresses. This is like a ‘free soft tapeout’ we can run as many times as needed. This approach saves development time and money while dramatically increasing confidence in our design and product release timeline.”
Dr. Joachim Peerlings, Vice President and General Manager of Keysight’s Network and Data Center Solutions Group, said: “By accelerating and de-risking chip development, Keysight USPA delivers a new end-to-end solution that meets the challenges of leading-edge designs in a very high-cost environment. This powerful platform gives chip developers a digital twin of their future silicon device, allowing them to fully validate their designs and algorithms before incurring the expense and risk of a tapeout.”
Suggested Items
Real Time with… IPC APEX EXPO 2024: My Role as a Technology Solutions Director
05/02/2024 | Real Time with...IPC APEX EXPOPeter Tranitz, senior director of technology solutions at IPC, shares insights into his role as the design initiative lead. He details his advocacy work, industry support, and the responsibilities of the design initiative committee. The conversation also covers the revamping of standards, the IPC Design Competition, and the implementation of design rules in software tools.
Real Time with… IPC APEX EXPO 2024: Ventec Discusses New Pro-bond Family of Advanced Products
05/01/2024 | Real Time with...IPC APEX EXPOChris Hanson, Ventec's Global Head of IMS Technology, outlines the launch of four pro-bond formulas that deliver an outstanding combination of low dissipation factor (Df) with a dielectric constant (Dk) range to maximize the design window for critical PCB parameters. As Chris points out, Pro-bond is designed for low-loss, high-speed applications, while thermal-bond dissipates heat from a component through the board to a heat sink.
IPC's Vision for Empowering PCB Design Engineers
04/30/2024 | Robert Erickson, IPCAs architects of innovation, printed circuit board designers are tasked with translating increasingly complex concepts into tangible designs that power our modern world. IPC provides the necessary community, standards framework, and education to prepare these pioneers as they explore the boundaries of what’s possible, equipping engineers with the knowledge, skills, and resources required to thrive in an increasingly dynamic field.
On the Line With… Talks With Cadence Expert on SI/PI for PCB Designers
05/02/2024 | I-Connect007In “PCB 3.0: A New Design Methodology—SI/PI for PCB Designers,” subject matter expert Brad Griffin, Cadence Design Systems, discusses how an intelligent system design methodology can move some signal and power integrity decision-making into the physical design space, offering real-time feedback.
iNEMI Packaging Tech Topic Series: Role of EDA in Advanced Semiconductor Packaging
04/26/2024 | iNEMIAdvanced semiconductor packaging with heterogenous integration has made on-package integration of multiple chips a crucial part of finding alternatives to transistor scaling. Historically, EDA tools for front-end and back-end design have evolved separately; however, design complexity and the increased number of die-to-die or die-to-substrate interconnections has led to the need for EDA tools that can support integration of overall design planning, implementation, and system analysis in a single cockpit.