Designers Notebook: Embedding Resistor Elements—Part 2

The decision to embed passive components within the PCB structure is commonly prompted by two key barriers: restricted surface area and interconnect complexity. The PCB’s functionality may also require a significant number of semiconductor packages, often requiring very close coupling to meet their target performance potential. Regarding surface area challenges, many companies are confronted with the need to reduce end-product size to maintain a competitive edge in a particular market, or to satisfy the anticipated needs of their customer base.

Over 70% of the components occupying space on a typical printed circuit board are passive (resistors, capacitors, inductors). Although most passive components are minimal in size, they can occupy up to 50% of the board’s surface area. Transferring most of the resistor elements onto the subsurface layers of the PCB will enable the designer the opportunity to optimize semiconductor placement, reduce circuit board size (typical of that illustrated in Figure 1), and ultimately achieve the most efficient interconnect between principal functions. 

Vern_Fig1_cap.jpg
As an alternative to the thick-film resistor process detailed in Part 1 of this topic, a significant number of PCB fabricators are offering embedded thin-film resistor capability. In comparing the thick-film resistor forming process, photo-lithography has replaced the printing and dispensing of paste-like resist materials to define the embedded resistors’ geometry. Many circuit board fabricators prefer the coated copper foil technology because the composite material’s base value range is more precise than the deposited thick-film alternative, ensuring that the value and tolerance of the formed resistor element is more likely to meet customer expectation.

Base Materials for Thin-Film Resistor Forming
To begin, a resistive alloy coating is deposited onto copper foil to create the base material for embedded resistor applications. The resistive alloy is electrodeposited or deposited onto the copper foil using a roll-to-roll sputtering process. Resistive alloy thickness determines the overall resistance value (ohms/sq.) of the coated copper foil. Alloys commonly applied for embedded resistor applications include nickel phosphorous (NiP), chromium silicon monoxide (CrSiO), nickel chromium aluminum silicon (NCAS), and nickel chromium (NiCr). The sheet resistance of nickel-chrome alloy film containing 20% chromium, as an example, will furnish the designer with a resistance range as high as 3 K-ohms.

Resistor Element Planning
Typical of the discrete resistor element, the formed resistor will span the area between two copper lands. The shape of the resistance material between the copper lands can be a simple square, a series of squares to form a rectangle, or a shape designed to maximize resistor element length while minimizing area.

Initial planning:

  1. Identify resistors for embedding.
  2. Establish R-value and target tolerance.
  3. Determine power rating requirement.
  4. Define finished element geometry.
  5. Select location (layer) and orientation.

The power dissipation is the rate at which resist energy is lost in elements. The power capability for embedded resistors will depend on the physical size of the resistor elements, temperature rating of the surrounding substrate materials, and the board stack-up. In the end it boils down to how the heat generated is managed. Typical power dissipation for most thin-film resistor designs operating at an ambient of less than 70°C is approximately 1/10 to 1/8 watt.

Typical of the thick-film composites, the base values of the thin-film resist-coated copper foil sheet materials are based on a single square geometry. While terminating resistor values are predominantly 50 ohms, and pull-up resistors fall in a range between 1K ohm and 10K ohm, these base values can be extended to furnish significantly higher resistor elements.

Implementation:

  1.  Establish land pattern (termination) geometry.
  2.  Define overall element dimensions.
  3.  Select optimum element position.
  4.  Plan most efficient circuit interface.
  5.  Provide features for test probe access.

As noted, the “square” geometry represents the basic ohm value of the resistive material. The designer can increase the resistance value by simply extending the length of the resistor pattern with additional squares or partial square segments (Figure 2). 

Vern_Fig2_cap.jpgThe resist-coated copper foil will become an integral part of the multilayer circuit board construction that, when processed, will furnish both formed resistor elements and provide general interconnect functions. The formed NiP resistor element examples (Figure 3) represent a subsurface interconnect layer prepared for lamination within a multilayer PCB. 

Vern_Fig3_cap.jpgAfter chemically removing copper and defining the resistor image, the now exposed nickel-phosphorous resistive material exhibits a matte grey finish.

To enable efficient utilization of the primary base value of the coated foils, the element geometry can be extended further in length to provide a broad range of resistor values. When the resistor element length becomes too long, however, it can restrict or block efficient circuit routing paths. To compress the surface area required for the more complex resistor elements, it is common practice to compress the physical area using a “serpentine” configuration typical of that exhibited in Figure 4.  

Vern_Fig4_cap.jpgThe design rules for the serpentine-configured resistor pattern are significantly different than the straight bar configuration detailed above. When developing the resistor element in a serpentine configuration the designer must adjust the basic value at each corner of the serpentine pattern. The square geometry located at each corner transition will furnish a value that is only one-half the resist material’s base value. The 19-square resistor pattern illustrated in Figure 5 represents a 15K-ohm resistor utilizing 1K-ohm base value material. 

Vern_fig5_cap.jpg
Regarding individual resistor tolerance control, thin-film material suppliers note that most circuit board fabricators will anticipate a resistor tolerance at or less than 20%. The resulting tolerance will be dependent on the precision of the image and etch process. Precise etch control will repeatedly produce resistors with a tolerance range encompassed by what the fabricator can maintain on controlled impedance lines and the published sheet tolerance. Variation of the tolerance can be minimized by maintaining a uniform element width (> 200-micron) for the resistor patterns and fine-tuning the resistor element length to achieve the required target resistor value. But the designer must keep in mind that over specifying resistor tolerance will likely impact processing costs.

Sourcing Thin-Film Resistive Materials
Resist coating can be furnished on any copper foil thickness, but thicknesses of 12 µm, 18 µm (0.5 oz) and 35 µm (1 oz) are likely to be more available because they are commonly selected for a wide range of multilayer organic circuit board applications. The two leading suppliers of the copper foils furnished with the resistive coatings in North America are Ohmega Technologies LLC. and Ticer Technologies.[1]

Materials provided for resistor formation from Ohmega Technologies are described as a subtractive technology where the base material preparation begins with a thin-film resist-coated copper foil laminated onto a glass-reinforced dielectric. In preparation, the company first electrodeposits a thin coating of nickel phosphorous (NiP) alloy onto the copper foil’s matte or tooth side. Base resist values of the Ohmega coated copper foils range from 10 Ω/sq to 377 Ω/sq (Table 1). 

Vern_Table1_cap.jpg
The power dissipation is the rate at which resist energy is lost in elements. The power capability for embedded resistors will depend on the physical size of the resistor elements, temperature rating of the surrounding substrate materials, and the board stack-up. In the end it boils down to how the heat generated is managed. Typical power dissipation for most thin-film resistor designs operating at an ambient of less than 70 °C is approximately 1/10 to 1/8 watt.

Coated foil materials can be furnished as a foil only product or pre-laminated to a variety of standard FR-4, polyimide, or more specialized microwave substrate materials. The pre-laminated material can be furnished directly from Ohmega Technologies as well as other sources, including Arlon, Rogers, and Taconic. The company also offers a NiP material with a sheet resistivity of 377 ohms per square, which was developed for a range of specialized applications that include high impedance and frequency selective surfaces, antenna arrays, or as radar absorbing materials for resistive cards.

Three variations of resistive-coated thin-film on copper foils are available from Ticer Technologies that provide a specific range of resist coatings: nickel-chromium (NiCr), nickel chromium-aluminum-silicon (NCAS) and chromium-silicon-monoxide (CrSiO). Individually, these alloy compositions can furnish a broad range of base resist values from 25 ohms to 1K ohms. Table 2 details the sheet resistance value range, tolerance and the maximum power dissipation factor for the three resistance alloy compositions noted. 

Vern_table2_cap.jpg
Ticer Technologies resistive-coated copper foil material is furnished in sheet form or as a product pre-laminated onto standard ROHS-compliant FR-4 glass-reinforced resin material or any number of reinforced specialty resins from a vast network of global material suppliers.

Resistor Process Sequence
The resistor forming process will include two or three etch steps, depending on the resistor alloy selected. The process flow illustrated in Figure 6 from Ticer Technologies represents a two-stage chemical etching sequence for their nickel chromium (NiCr) resistive material. 

Vern_Fig6_cap.jpg
With respect to circuit layer preparation, fabricators are able to image and chemically etch the circuit layers using standard subtractive PCB processing. As far as chemistry, the printed circuit board industry commonly employs cupric chloride etchants for the primary circuit image and resistive layer width definition. A second etch step is required to selectively remove copper to define the length of the resistor elements. This process requires a different chemistry to ensure only copper removal without altering or degrading the remaining resistive element geometry.

Power Dissipation
As far as handling power, the manufacturers state that power density is defined as the total power dissipated divided by the effective surface area. The power density of the resistor element increases as the area decreases. All other conditions illustrate that for the same power input, the temperature rise will depend on the area of the resistor. In other words, the resistors with a larger surface area can dissipate more power than a narrow geometry, provided that all conditions remain the same. If space is available, design the resistor element to be as wide as possible. Additionally, when the resistors are buried within the layers of the circuit board, the physical and thermal characteristics of the substrate material (the total thickness of the substrate and the collective number of copper layers) will directly affect heat dissipation from the fully assembled circuit board.

Omega Technologies notes that electrical current should not exceed the rated current-carrying capacity of the resistor because excessive current could cause permanent damage to the formed resistor element.[2]

In-Process Testing
Prior to further circuit layer lamination, the resistor elements’ value and tolerance must be validated. The “flying probe” test is widely used to validate the embedded resistor elements’ target value before lamination of additional circuit layers. Most flying probe testers can also perform signal integrity testing as well as identify the location of opens and shorts. To enable test probe access, dedicated land features must be provided for each formed resistor element. Lands provided for test probe access must not be arranged in a way that would require probes to cross over or contact other probes. When laser trimming is required to fine-tune a resistor element, the probe contact must not interfere with laser access while making a trim. For best test and trim accuracies, the test lands should be near to the resistor-to-circuit termination point to ensure precise resistor value measurement.

When developing land geometry for test-probe access, probe tip shape and dimensions will determine the minimum land size. Test system manufacturers state that probes have a placement tolerance of 50 μm (0.002”) in each of the X, Y, and Z axes. The land pattern diameter must be greater than the probe tip to accommodate probe positional tolerances and allow for uniform probe pressure and pad scrub. First-time users should refer to their circuit board supplier to determine the suitability of their test equipment and availability of the required software for testing the embedded resistor elements.

Design Tools
Most software developers are currently furnishing the necessary tools to implement the embedded resistor elements within the multilayer circuit board. Material suppliers suggest that the CAD designer consider using Mentor, Allegro, Intergraph, and PAD Power PCB in conjunction with an Excel program to aid in developing the more complex resistor element geometries. While several resistor elements will likely remain on the outer surface of the finished circuit board, the embedded resistors will require a unique reference designator to avoid procurement errors. For example, a surface-mounted resistor will be defined as R110 while the embedded or buried resistor will be labeled BR110 on the schematic diagram and material list.

Implementation Issues and Concerns
Formed passive resistor element values and tolerance that range between 5–10% will likely meet the operational criteria of the final product but altering the value after lamination will not be an option. Due to the physical stresses experienced during PCB lamination and assembly processing, target values of resistors may drift outside the specified resistance target, and laser trimming will not be practical. When the specified values of the resistor elements require tolerance in the 1-2% range, I strongly advise the circuit board designer to retain these higher precision resistors as discrete surface mount components for placement onto the circuit board’s outer surface(s).

References

  1. Ohmega Technologies has been acquired by Quantic Electronics, a business unit of Arcline Investments which focuses on specialty component materials. More recently, Quantic also acquired Ticer Technologies. The company stated that it plans to maintain multi-plant resistive foil operations for both OhmegaPly and Ticer TCR materials. 
  2. For more information refer to the Power Dissipation Guidelines contained within the Resistor Calculators on both Ticer’s and Ohmega’s websites.

This column originally appeared in the June 2021 issue of Design007 Magazine.

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2021

Designers Notebook: Embedding Resistor Elements—Part 2

06-15-2021

As an alternative to the thick-film resistor process detailed in Part 1, a significant number of PCB fabricators are offering embedded thin-film resistor capability. Read Part 2 here.

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Designers Notebook: The 'New and Growing' Embedded Resistors

04-19-2021

Why is embedded resistor technology considered to be “new” and “growing” despite decades of history? In fact, a broad number of established PCB fabricators are knowledgeable about the materials and processes for embedding resistor elements but not all may be prepared to alter procedures established for their more conventional multilayer circuit board customer base.

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Designers Notebook: Developing Panel Level Semiconductor Packaging

02-22-2021

While semiconductor packaging has traditionally utilized a narrow strip of organic copper-clad organic-based laminate and wire-bond processing for the single-die BGA. Companies furnishing devices for high-volume markets are now implementing very fine-pitch alloy bumped flip-chip package technologies that enable face-down interface.

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2020

Designers Notebook: Panel-level Semiconductor Package Design Challenges

05-15-2020

Semiconductor package specialists continually work to improve high-volume manufacturing process efficiencies while reducing manufacturing costs. A majority of the commercial semiconductors are built-up on the surface of a circular-shaped silicon wafer with metalized terminal features at their perimeter to accommodate wire-bond interface with a lead-frame or package substrate. Vern Solberg explains.

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Designers Notebook: Design Challenges for Developing High-density 2.5D Interposers, Part 2

01-29-2020

In Part 2 of his column series on design challenges for high-density 2.5D interposers, Vern Solberg discusses primary base materials for 2.5D interposer applications, design guidelines, technical challenges, and key planning issues.

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Designers Notebook: PCB Design and HD Semiconductor Packaging

01-15-2020

To better meet their performance and miniaturization goals, manufacturers are looking for higher functionality for their semiconductor packages. For that reason, many manufacturers will rely heavily on more innovative IC package solutions, often integrating a number of already proven functional elements within a single-package outline. Vern Solberg covers how this and more impact PCB design and HD semiconductor packaging.

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2019

Designers Notebook: Focus of Interest at SMTAI 2019—Low-temperature Solder

10-03-2019

Both suppliers and users of solder materials participated in discussions at SMTAI 2019 related to low-temperature solder (LTS). The solder supply companies present had a wide range of material compositions that employed elements of bismuth or indium to reduce the liquidus temperature of the alloy during the joining process. Key issues that user companies are concerned with are the lower-temperature alloys selected must be reliable and exhibit shear strength, creep resistance, and resistance to thermal fatigue for the duration of the product’s life cycle.

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Designers Notebook: Embedding Components, Part 7—Semiconductor Placement and Termination Methodologies

03-11-2019

Progress in developing high-density embedded-component substrate capability has accelerated through the cooperation and joint development programs between many government and industry organizations and technical universities. In addition to these joint development programs, several independent laboratories and package assembly service providers have developed a number of proprietary processes for embedding the uncased semiconductor elements.

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Embedding Components, Part 6: Preparation for Active Semiconductor Elements

01-10-2019

Designers are well aware that a shorter circuit path between the individual die elements, the greater the signal transmission speed, which significantly reduces inductance. By embedding the semiconductors on an inner layer directly in line with related semiconductor packages mounted on the outer surface, the conductor interface distance between die elements will be minimized.

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2018

Embedding Components, Part 5: Alternative Termination Methodologies and Surface Plating Variations

12-19-2018

Because they are furnished with a very thin profile, resistor and capacitor components with different values can be mounted directly onto land patterns on a subsurface layer of the printed circuit structure. However, handling and placing of these small components requires systems with a high level of positional accuracy. Interconnection can be accomplished using either deposited solder paste and reflow processing or applying a conductive polymer material. Due to the extremely small land pattern geometries required for mounting the miniature passive components, companies commonly rely on precision dispensing these materials.

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Embedding Components, Part 4: Passive Component Selection and Land Pattern Development

11-29-2018

As noted in Part 3 of this series, a broad range of discrete passive component elements are candidates for embedding, but the decision to embed these component elements within the multilayer circuit structure must be made early in the design process. While many of these components are easy candidates for integrating into the substrate, others may not be suitable, or they are difficult to rationalize because they involve more complex process methodology.

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Embedding Components, Part 3: Implementing Discrete Passive Devices

11-15-2018

Most of the passive components used in electronics are discrete surface mount components configured to mount onto land patterns furnished on the surface of a PC board. Designers have several choices for providing passive functions in a system design, such as discrete surface-mounted passives, array passives or passive networks, integrated (Rs and Cs) passive devices, and embedded discrete passive components.

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Designers Notebook: Strategies for High-Density PCBs

01-01-2018

As hand-held and portable electronic products and their circuit boards continue to shrink in size, the designer is faced with solving the physical differences between traditional printed board fabrication and what’s commonly referred to as HDI processing. The primary driver for HDI is the increased complexity of the more advanced semiconductor package technology. These differences can be greater than one order of magnitude in interconnection density.

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2017

Strategies for High-Density PCBs

11-27-2017

As hand-held and portable electronic products and their circuit boards continue to shrink in size, the designer is faced with solving the physical differences between traditional printed board fabrication and what’s commonly referred to as high-density interconnect (HDI) processing.

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Embedding Components, Part 2

07-30-2017

Technology and processes for embedding capacitor and inductor elements rely on several unique methodologies. Regarding providing capacitor functions, IPC-4821 defines two methodologies for forming capacitor elements within the PCB structure: laminate-based (copper-dielectric-copper) or planar process and non-laminate process using deposited dielectric materials.

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Embedding Components, Part 1

06-30-2017

The printed circuit has traditionally served as the platform for mounting and interconnecting active and passive components on the outer surfaces. Companies attempting to improve functionality and minimize space are now considering embedding a broad range of these components within the circuit structure. Both uncased active and passive component elements are candidates for embedding but the decision to embed components within the multilayer circuit structure must be made early in the design process.

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2016

Specifying Lead-Free Compatible Surface Finish and Coating for Solderability and Surface Protection

07-06-2016

A majority of the components furnished for electronic assembly are designed for solder attachment to metalized land patterns specifically designed for each device type. Providing a solder process-compatible surface finish on these land patterns is vital...

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Flexible and Rigid-Flex Circuit Design Principles, Part 6

05-26-2016

The designer is generally under pressure to release the documentation and get the flexible circuit into production. There is, however, a great deal at risk. Setting up for medium-to-high volume manufacturing requires significant physical and monetary resources. To avoid potential heat from management, the designer must insist on prototyping the product and a thorough design review prior to release.

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Flexible and Rigid-Flex Circuit Design Principles, Part 5

04-27-2016

The outline profile of the flexible circuit is seldom uniform. One of the primary advantages of the flexible design is that the outline can be sculpted to fit into very oblique shapes. In this column, Vern Solberg focuses on outline planning, physical reinforcement, and accommodating bends and folds in flexible and rigid-flex circuits.

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Flexible and Rigid-Flex Circuit Design Principles, Part 4

03-30-2016

All of the design rules for the glass reinforced-portion of the board (land pattern geometry for mounting surface mount devices, solder mask and the like) are now well-established. One unique facet of fabricating the rigid-flex product is how the flexible portion of the circuit is incorporated with the rigid portion of the circuit. As a general rule for multilayer PCB design, furnish a balanced structure by building up the circuit layers in pairs (4, 6, 8 and so on).

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Flexible and Rigid-Flex Circuit Design Principles, Part 3

03-02-2016

This column focuses on methods for specifying base materials, and also address copper foil variations and fabrication documentation. It is important to research the various products in order to choose the one that best meets the design requirements.

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Flex and Rigid-Flex Circuit Design Principles, Part 2

02-19-2016

Flexible circuits are commonly developed to replace ordinary printed circuit board assemblies that rely on connectors and hardwire for interconnect.

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Flex and Rigid-Flex Circuit Design Principles, Part 1

01-27-2016

Flexible circuits represent an advanced approach to total electronics packaging, typically occupying a niche that replaces ordinary printed circuit board assemblies and the hard-wire interface needed to join assemblies.

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2005

PCB Designers Notebook: Flexible Circuit Design

01-03-2005

The flexible circuit was originally used as a conductive element for interfacing signals from one electronics assembly to another.

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